The present invention relates to digital circuits, and more particularly to a data delay circuit for arbitrarily controlling a delay for a serial digital data signal.
A digital circuit generally has many blocks coupled together and, when a digital data signal is sent from one block to the next block, it is sometimes necessary to delay the digital data signal by a given amount. Japanese Patent Publication No. H06-177722 (unexamined) discloses an example of such delay technology. A serial-to-parallel shift register converts a serial digital data signal into a four-bit parallel digital data signal, each bit being provided to a separate one of four shift registers respectively. The clock speed of each shift register can be one fourth of a master clock speed so that inexpensive ones are used. Each of the four shift registers has eight delay outputs. A multiplexer is provided for each of the four shift registers so that there are four multiplexers in total. The multiplexers are controlled to select the same delay output from the four shift registers at the same time. Which delay output of the shift registers the corresponding multiplexers select determines the delay amount of the digital data. A parallel-to-serial shift register converts the digital data from the four multiplexers into a serial digital data signal that is delayed relative to the original serial digital data signal by a given time determined by the multiplexers.
Japanese Patent Publication No. 08-129878 (examined) also discloses similar technology. It converts a serial digital data signal into a parallel digital data signal, each bit of which is delayed, and the delayed bits are converted into a serial digital data signal again to achieve the desired serial digital data signal delay.
All of the above-described prior art produce a delayed serial digital data signal that is synchronized with the same clock as that of the original serial digital data signal, this clock being called a master clock or a system clock. This is because the serial digital data signal is expected to maintain the same timing in the next block of the digital circuit. The technology disclosed in the above Japanese Patent Publication No. 08-129878 is typically used for television signal processing in such products as a frame synchronizer, etc.
There are other applications in which the delay of the serial digital data signal is not an integral multiple of the master clock cycle or is not synchronized with the master clock. One example is the generation of a test digital data signal for use in jitter tolerance testing the digital circuit. In jitter tolerance testing the test digital data signal in which jitter is intentionally introduced is provided to a circuit under test to determine how much jitter is acceptable for proper operation of the circuit under test. The digital data signal for jitter tolerance testing may be produced by delaying a normal digital data signal that is usually provided to the circuit under test. But the jittered digital data signal is not necessarily synchronized with the master clock.
What is desired is a data delay circuit that is useful for delaying a serial digital data signal that is not necessarily synchronized with a master clock, that is simple, and that allows continual (analog-like) change of the delay amount of the serial digital data signal to produce a serial digital data signal that includes jitter.
Accordingly the present invention provides a data delay circuit that produces a serial digital data signal with an arbitrary amount of delay when it converts a parallel digital data signal into the serial digital data signal. The parallel digital data signal may be supplied directly from a memory or from the conversion of a serial digital data signal via a serial-to-parallel converter. The data delay circuit may include a voltage controlled delay device that changes a delay amount continuously according to a control signal. The data delay circuit receives a parallel data clock and provides a delayed parallel data clock according to the control signal. A parallel-to-serial converter converts the parallel digital data signal into the serial digital data signal using the delayed parallel data clock. A control means provides the control signal to the data delay circuit to control the amount of delay for the serial digital data signal. The parallel-to-serial converter may have a phase-locked clock generator. The phase-locked clock generator produces a serial data clock having a frequency that is an integer multiple of the parallel data clock frequency, the integer multiple corresponding to the number of bits per word of the parallel digital data signal. The phase of the serial data clock is locked to that of the delayed parallel data clock. The data delay circuit may further have a data buffer that temporally stores the parallel digital data signal when a serial-to-parallel converter is used as a means for providing the parallel digital data signal from an input serial digital data signal. The data buffer also may be used if a memory is used as the parallel digital data signal source. The control signal provided to the data delay circuit may not be constant and may change continuously like a sine wave, for example, to allow the delay of the serial digital data signal to also change continuously to produce a serial digital data signal that includes jitter.
The objects, advantages and other novel features of the present invention are apparent from the following detailed description when read in conjunction with the appended claims and attached drawing.